‹ Wednesday, July 18, 2018 › | |
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›9:00 (1h30)
Design and Verification of Safe and Secure VLSI Systems
Prof. Juan-Carlos Ruiz, University Politecnica of Valence ›10:30 (30min)
›11:00 (1h)
›12:00 (1h30)
›13:30 (1h30)
›15:00 (1h)
›16:00 (30min)
›16:30 (1h30)
›18:00 (2h)
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Session | Speech | Logistics | Break | Tour |